This invention relates to integrated circuit packages and more particularly to chip scale packages.
Chip scale packages (CSP) represent a new miniature type of semiconductor packaging used to address the issue of I/O densification and size in electronic products, especially for consumer type products such as telephones, pagers, video cameras, etc. With the trend moving to packing more and more features into decreasing product envelopes, utilizing ever smaller electronic components to improve upon size and feature densification is a constant formidable challenge for manufacturers of consumer and related articles.
Typically, in the electronic component world, integrated circuits (IC) are fabricated on a semiconductor substrate, known as a chip or die and most commonly made of silicon. This silicon IC chip or die is then typically mounted into a larger container (package) which serves 1) to provide effective enlargement of the distance (pitch) between the I/O contacts of the silicon suitable for attachment to printed circuit boards (PCB) in real world applications and 2) as a hermetic container to protect the IC from handling abuse.
Although recently the semiconductor industry has introduced reduced package sizes, such as those in area array format vs. most typical peripheral attach of the input and output (I/O) terminals such as in lead frame construction, the area on the PCB occupied by the package is much larger than the area occupied in the package by the silicon.
Many companies today are trying to solve the problems of utilizing the IC chip or die directly to the PCB, i.e., flip chip, without the use of an intermediate package. After all, the silicon chip represents the smallest size possible for the IC package. Although some manufacturers are using this technology with varying degrees of success in a few products today, numerous technical challenges not yet overcome effectively block the widespread use of flip chip.
Chip scale packages were invented to provide an alternative solution to flip chip. They are not hindered by most of the problems facing flip chip. Although not yet defined as a semiconductor industry standard, a chip scale package is currently loosely defined as a package that is within 20% larger than the IC itself, thus approaching the smallest size possible for a package (the IC chip).
Trade publications such as "Known Good Die and Chip Scale Packaging" published in the U.K. by BPA (1995 and 1996), have identified approximately 20 companies that are currently preparing to manufacture their own configuration of CSPs. Over 25 different configurations are represented.
The 25 or so different CSP types can be placed into several distinct categories. One category of interest for the applicants is the Rigid substrate type. Rigid substrates are typically characterized by the attachment of the silicon IC die to a rigid carrier or substrate (e.g., ceramic (organic types), and FR4, BT (inorganic, laminate types)) using a high temperature solder attach process which is well known in the industry. The carrier contains the appropriate electrical traces which route the I/O points on the IC to the opposite side of the rigid carrier (from the IC attachment side). The traces are run to appropriate I/O points (typically solder balls) on this opposite, or backside, of the carrier. The opposite side solder balls are then used in the solder attachment of the IC/carrier package to a matching electrical site (e.g., to a ball pattern) on the product PCB. This solder attach method is also well known in the industry.
Because the material of the IC and the carrier are different and expand at different rates when heated (when power is applied to the IC), severe stress is introduced to the solder connections between the silicon and the carrier. The stress caused by the thermal expansion coefficient mismatch as power to the IC is cycled on and off typically causes mechanical failure at one or more of the solder joints, in turn causing electrical failure of the product. To alleviate this problem and distribute the stresses, a polymeric filler or underencapsulant is introduced in liquid form by capillary action into the typical 2-mil to 4-mil gap or standoff between the circuit side of the chip and the contact side of the substrate. The "underfill" completely fills the volume under the IC around all the solder joints. It cures to a rigid form via time, temperature, ultraviolet exposure, or some combination of these or other variables.
To insure proper coverage of the area under the IC, enough underfill is supplied so that it runs out along the perimeter of the silicon. In the construction of the rigid substrate CSPs, the carrier is slightly (typically approaching 20%) larger in size in the plane of the IC than the IC chip itself. A reason for this is that the underfill material needs a "ledge" to sit on during application (as it flows into the gap). A second reason is that the underfill material does not cure perpendicular to the parallel planes of the IC and the carrier at the perimeter of the IC; instead, it forms a fillet at the perimeter, which is asymmetric about the gap. A properly formed fillet is believed to be important to the reliability enhancement added by the underencapsulant. With the orientation of the package during construction having the IC on the topside, the fillet is typically directly attached to the underside of the IC at its edge and then extending downward, attaching itself onto the rigid carrier, but extending a small distance outward from the area on the carrier defined by the IC chip. A cross-section would reveal that the fillet creates a smooth curve from top to bottom, being slightly concave inward. Thus, for this type of chip scale package, the area ratio between the silicon chip and the carrier is less than 1:1, caused by the additional carrier or substrate area required.
Only one of the technologies described in the literature and known to applicants have a construction in which the package and IC chip are the same size. This technology offered by Tessera, of San Jose, Calif., provides a nearly 1:1 package by mounting the chip on a flexible polyimide tape. Although this size package is advantageous, it is very expensive to make due to the specialized tape required and the complexity of construction using a flexible carrier. Applicants are unaware of any other attempts to provide a 1:1 silicon/package CSP in a type different than that offered by Tessera.
Accordingly, a need remains for a simpler, smaller and less expensive chip scale package design and method of making.